1. Field of the Invention
This invention relates generally to digital logic circuits, and more particularly, to a MOSFET incrementer circuit.
2. Description of the Prior Art
Within integrated circuit microprocessors, registers are often provided for storing a digital value. Often a register will have a dedicated purpose, as for implementing a timer or a program counter, which generally requires that the digital value be incremented by one at a periodic rate. Although microprocessors generally contain an arithmetic-logic unit which is capable of adding numbers, a separate incrementer circuit is often provided to increment the digital value in the dedicated register in order to avoid using the arithmetic-logic unit for this purpose. The addition of a separate incrementer circuit allows the arithmetic-logic unit to perform other microprocessor operations simultaneously with the incrementing of the dedicated register.
An example of a prior art MOSFET incrementer circuit may be found in U.S. Pat. No. 4,030,079 "Processor Including Incrementer and Program Register Structure" to Bennett et al and assigned to the assignee of the present invention. Typically the register containing the value to be incremented includes a plurality of bit stages, and the incrementer has a corresponding number of increment stages. During a first clock period, a first clock signal enables a plurality of precharge devices which precharge a plurality of nodes to a positive voltage. During a second clock period, a first node is discharged to ground in order to toggle the least significant bit. A plurality of series connected MOSFET devices are coupled between successive nodes within the incrementer. If the least significant bit is a high level prior to being toggled, then the first series-connected MOSFET device is enabled and the node for the next least significant bit is also discharged, thereby causing the next least significant bit to also be toggled by the incrementer.
Occasionally, a microprocessor must avoid incrementing the contents of the register. This may occur for example when the microprocessor detects an interrupt condition. However, this condition might not be detected until the second portion of the clock period at which time some of the incrementer nodes have already been discharged. Thus, in order to avoid the increment operation, it is necessary to once again charge the incrementer nodes to a positive voltage prior to transferring the result of the incrementer into the register.
In the prior art, control logic generates a first signal for enabling the precharge MOSFET devices to precharge the incrementer nodes, and the control logic generates a second control signal or carry-in for allowing an increment operation to be performed. As the number of conditions which determine whether or not an increment operation will be performed is increased, the complexity of the logic circuitry for determining the first and second control signals correspondingly increases.